Distributed bus arbitration for a multiprocessor system

Patent · Tue Mar 08 04:00:00 EST 1988

OSTI ID:5039774

Marin, J S

A system for providing bus arbitration for at least two processors having a common clock signal is described comprising: an asynchronous arbitration signal line connecting the processors into a ring; an asynchronous cycle grant signal line connecting the processors into a ring; arbitration control means located in each processor and coupled to the arbitration signal line for determining which processor will control arbitration for bus access on a following clock cycle, wherein the control means includes means for selecting an arbitration state of the control means; means for storing a bit indicating whether the processor has arbitration mastership; and logic means coupled to the asynchronous signal line, to the arbitration state selecting means, and to the bit storing means, for determining whether the processor will take arbitration mastership during the next cycle; cycle grant control means in each processor and coupled to the cycle grant signal line for determining which processor will have bus access on the following clock cycle.

• Assignee: Texas Instruments Incorporated, Dallas, TX
• Patent Number(s): US 4730268
• OSTI ID: 5039774
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
ARTIFICIAL INTELLIGENCE
COMPUTERS
DATA PROCESSING
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
LOGIC CIRCUITS
MEMORY DEVICES
MEMORY MANAGEMENT
PROCESSING
SIGNAL CONDITIONING
SUPERCOMPUTERS