Fair arbitration technique for a split transaction bus in a multiprocessor computer system
Patent
·
OSTI ID:6385478
This patent describes a computer system comprising modules and bus means commonly connected to all of the modules for conducting information signals between the modules, each module including means for transmitting information signals as a transfer over the bus means and while doing so functioning as a master module, each module also including means for receiving the transfer of information signals from the bus means and while doing so functioning as a slave module, a predetermined number less than all of the modules including means for initiating a transfer over the bus means in response to exogenous or internally generated events and thereby functioning as an initiator module, each module of other than the initiator modules including means for transmitting a transfer on the bus means only in response to a previous transfer transmitted by an initiator module and thereby functioning as a responder module, means associated with each module for assigning a predetermined priority to each module, the priorities of each module being different from one another, each responder module having a higher priority than any initiator module, means associated with each module for asserting a request signal indicative of the predetermined priority of that module upon that module desiring to become a master module for transmitting a transfer over the bus means, and an improved arbitration means connected to the bus means and responsive to the request signals and operative during each of sequential arbitration time periods fore determining which of the modules asserting request signals is to be granted exclusive access to the bus means as a master module for a bus predetermined time period to transmit a transfer to an addressed slave module.
- Assignee:
- Datapoint Corp., San Antonio, TX
- Patent Number(s):
- US 4785394
- OSTI ID:
- 6385478
- Country of Publication:
- United States
- Language:
- English
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