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Title: Arbitration in crossbar interconnect for low latency

Patent ·
OSTI ID:1083210

A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,370,551
Application Number:
12/684,287
OSTI ID:
1083210
Country of Publication:
United States
Language:
English

References (13)

Multi-master bus arbitration system in which the address and data lines of the bus may be separately granted to individual masters patent September 1996
Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses patent March 2000
Method and apparatus for allocating bus access rights in multimaster bus systems patent May 2008
Hierarchical bus structure and memory access protocol for multiprocessor systems patent December 2008
Device control register for a processor block patent June 2010
Processor local bus bridge for an embedded processor block core in an integrated circuit patent August 2011
Method and system for controlling transmission and execution of commands in an integrated circuit device patent April 2012
Arbiter having programmable arbitration points for undefined length burst accesses and method patent-application March 2005
Method of accessing memory via multiple slave ports patent-application December 2005
Data processing system with bus access retraction patent-application March 2006
Plural bus arbitrations per cycle via higher-frequency arbiter patent-application August 2006
Memory and Memory Communication System patent-application December 2007
Communication infrastructure for a data processing apparatus and a method of operation of such a communication infrastructure patent-application February 2011

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