Low delay and area efficient soft error correction in arbitration logic

Sugawara, Yutaka

Low delay and area efficient soft error correction in arbitration logic

Patent · Tue Sep 10 04:00:00 EDT 2013

OSTI ID:1093240

Sugawara, Yutaka

There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.

Research Organization:: International Business Machines Corp., Armonk, NY (United States)

Sponsoring Organization:: USDOE

Assignee:: International Business Machines Corporation (Armonk, NY)

Patent Number(s):: 8,533,567

Application Number:: 12/852,801

OSTI ID:: 1093240

Country of Publication:: United States

Language:: English

References (9)

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