Dual delay mode pipelined logic simulator

Patent · Tue Nov 22 04:00:00 EST 1988

OSTI ID:6337954

Nei, C C; Hafeman, D R; Fazakerly, W

This patent describes a logic simulator for simulating logic devices, each of the devices having some propagation delay or delays between changes in the input state of the device and a resultant change in the output state of the device. The simulator consists of: first storage means for storing a first propagation delay for each logic device to be simulated. The first delay being either zero or one simulated time unit; first simulating means coupled to the first storage for simulating a first zero and unit delay mode of operation utilizing the first stored delay; second storage means for storing a group of propagation delays for each of the simulated logic devices, the group of stored propagation delays being either zero, one unit, or multiple simulated time units; second simulating means coupled to the second storage means for simulating a zero, unit and multiple unit time wheel mode of operation utilizing the group of stored delays; control means for selecting from the first simulating means or the second simulating means either the first zero and unit delay mode of operation or the zero, unit and multiple unit time wheel mode of operation for the simulator.

• Assignee: Ikos Systems, Inc., Sunnyvale, CA
• Patent Number(s): US 4787061
• OSTI ID: 6337954
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ANALOG SYSTEMS
COMPUTER ARCHITECTURE
COMPUTERIZED CONTROL SYSTEMS
COMPUTERIZED SIMULATION
CONTROL SYSTEMS
DATA-FLOW PROCESSING
ELECTRONIC CIRCUITS
FUNCTIONAL MODELS
LOGIC CIRCUITS
MEMORY DEVICES
PROGRAMMING
SIMULATION
SIMULATORS