Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
This patent describes a data processing system comprising: a pair of independently operated processing units, each processing unit being operative to generate cache requests for data, each request including an address having first and second address portions; and a cache memory subsystem coupled to the pair of processing units for receiving the requests, the cache memory subsystem comprising: a directory store being divided equally into first and second pluralities of levels. The first and second levels each containing groups of storage locations, each location for storing the first address portion of a memory request generated by each of the pair of processing units allocated to the first and second levels and each different group of locations within the directory store levels being defined by a different one of the second address portions; a data store being divided equally into the same first and second levels as the directory store and each different group of locations with the data store levels being accessed by a different one of the second address portions; first and second accounting means being associated with the first and second levels of the cache store respectively and each accounting means containing the first level for storing information establishing the order for replacing locations within the levels on a least recently used basis; and multiple allocation memory (MAM) means including the first level of the groups of locations, each different group of locations being accessed by the second address portion.
- Assignee:
- Honeywell Bull Inc., Waltham, MA
- Patent Number(s):
- US 4785395
- OSTI ID:
- 6525256
- Country of Publication:
- United States
- Language:
- English
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