Virtual cache system using page level number generating cam to access other memories for processing requests relating to a page
This patent describes a cache memory for use in a multiprocessing system in which a number of processing units connect in common to share a main memory. The main memory is divided into a number of segments in which each segment includes a plurality of pages, each containing blocks, each of which has words, the cache memory being coupled to one of the processing units for providing fast access information fetched from the main memory in response to requests for information received from the one processing unit, each request including an input address for identifying the information words to be accessed from the cache memory. The cache memory consists of: content and addressable memories, each having an input and an output and containing locations for storing address information pertaining to each of a predetermined number of pages, a first one of the content addressable memories having the input coupled to receive the input address from the one processing unit; directly addressable random access memories, each having an input and an output and containing a plurality of locations for storing address, control and data information pertaining to each of the pages; a common internal bus connecting the output of the first one of the content addressable memories, the input of each of the remaining content addressable and the input of each of the directly addressable memories in common; and cache control means coupled to receive the requests from the one processing unit, the cache control means being operative in response to each request for information to apply a first portion of the input address.
- Assignee:
- Honeywell Bull Inc., Waltham, MA
- Patent Number(s):
- US 4785398
- OSTI ID:
- 6385452
- Country of Publication:
- United States
- Language:
- English
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