Address computation system for updating starting addresses of data arrays in an array processor within an instruction cycle
An address computation system for updating starting addresses of data arrays in an array processor having a data memory and means for executing an operational instruction during an instruction cycle is described comprising: (a) first address register means for storing a predetermined portion of a stating data address to be provided to the data memory; (b) second address register means for storing a predetermined portion of a current data address to be provided to the data memory; (c) output multiplexer means, responsive to the outputs of the first and second address register means and to an operational instruction, for selectively presenting to the data memory either the starting data address portion or the current data address portion; and (d) update combinational logic means, responsive to the output of the first address register means and to an operational instruction.
- Assignee:
- Tektronix, Inc., Beaverton, OR
- Patent Number(s):
- US 4704680
- OSTI ID:
- 5768181
- Country of Publication:
- United States
- Language:
- English
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