Instruction sequencer for parallel operation of functional units
This patent describes an instruction sequencer for programming parallel operations of functional units in response to an instruction stream comprising memory means for storing in selected locations in the memory means a plurality of instruction segments for programming operations of at least two of the functional units; an instruction address register adapted to be loaded with instruction addresses for selected locations in the memory means; memory addressing means operatively coupled to the memory means and the instruction address register and responsive to instruction addresses loaded in the address register for reading out instruction segments from addressed selected locations in the memory means in an instruction stream comprising instruction segments which include a selected instruction segment for programming operation of at least a predetermined one of the functional units; an instruction buffer register operatively coupled to the memory means for storing the instruction stream from the memory means; a rotating network means operatively coupled to the instruction buffer register for rotating the instruction stream to position a selected instruction segment thereof at a predetermined location in the rotating network means, the rotating network means including output means for transferring as an output therefrom the rotated instruction stream.
- Assignee:
- NOV; NOV-89-077307; EDB-89-164941
- Patent Number(s):
- US 4837678
- OSTI ID:
- 5393042
- Resource Relation:
- Patent File Date: 7 Apr 1987
- Country of Publication:
- United States
- Language:
- English
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