Fully symmetric cooled CMOS on (110) plane
- 300200
A new cooled CMOS device using dual-polysilicon gates, (110) Si substrates, lightly doped drains with doping concentrations of 10/sup 14/ cm/sup -2/, and no channel implant is described. It is found that the peak mobility of a p/sup +/ polysilicon gate pMOS transistor on a (110) plane is 1.6 time larger that that on a (100) plant at 77 {Kappa}. This pMOS transistor is very promising for use at 77 {Kappa} because of its steeper subthreshold slope and higher hole mobility. The design has realized fully symmetric cooled CMOS devices with 0.8/nm gates in which saturation currents and transconductances of both n and pMOS transistors have been almost equalized. This fully symmetric cooled CMOS increases the ring oscillator speed by a factor of 1.2 and allows flexible CMOS circuit design that allows effective use of NOR gates.
- OSTI ID:
- 5364722
- Journal Information:
- IEEE (Institute of Electrical and Electronics Engineers) Transactions on Electron Devices; (USA), Journal Name: IEEE (Institute of Electrical and Electronics Engineers) Transactions on Electron Devices; (USA) Vol. 36:8; ISSN IETDA; ISSN 0018-9383
- Country of Publication:
- United States
- Language:
- English
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Related Subjects
360603 -- Materials-- Properties
42 ENGINEERING
426000* -- Engineering-- Components
Electron Devices & Circuits-- (1990-)
COOLING
CRYSTAL DOPING
DESIGN
ELECTRONIC EQUIPMENT
ELEMENTS
EQUIPMENT
MATERIALS
MOS TRANSISTORS
N-TYPE CONDUCTORS
OSCILLATORS
P-TYPE CONDUCTORS
SEMICONDUCTOR DEVICES
SEMICONDUCTOR MATERIALS
SEMIMETALS
SILICON
SUBSTRATES
SYMMETRY
TRANSISTORS