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High-gain monolithic 3D CMOS inverter using layered semiconductors

Journal Article · · Applied Physics Letters
DOI:https://doi.org/10.1063/1.5004669· OSTI ID:1642668
 [1];  [1];  [1];  [1]
  1. Univ. of California, Berkeley, CA (United States)
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Here, we experimentally demonstrate a monolithic 3D integrated complementary metal oxide semiconductor (CMOS) inverter using layered transition metal dichalcogenide semiconductor N-channel (NMOS) and P-channel (PMOS) MOSFETs, which are sequentially integrated on two levels. The two devices share a common gate. Molybdenum disulphide and tungsten diselenide are used as channel materials for NMOS and PMOS, respectively, with an ON-to-OFF current ratio (ION/IOFF) greater than 106 and electron and hole mobilities of 37 and 236 cm2/Vs, respectively. The voltage gain of the monolithic 3D inverter is about 45 V/V at a supply voltage of 1.5 V and a gate length of 1 μm. This is the highest reported gain at the smallest gate length and the lowest supply voltage for any 3D integrated CMOS inverter using any layered semiconductor.
Research Organization:
Lawrence Berkeley National Laboratory (LBNL), Berkeley, CA (United States)
Sponsoring Organization:
Applied Materials, Inc.; Entegris, Inc.; USDOE Office of Science (SC), Basic Energy Sciences (BES), Materials Sciences & Engineering Division
Grant/Contract Number:
AC02-05CH11231
OSTI ID:
1642668
Journal Information:
Applied Physics Letters, Journal Name: Applied Physics Letters Journal Issue: 22 Vol. 111; ISSN 0003-6951
Publisher:
American Institute of Physics (AIP)Copyright Statement
Country of Publication:
United States
Language:
English

References (47)

Ultrathin Silicon Circuits With Strain-Isolation Layers and Mesh Layouts for High-Performance Electronics on Fabric, Vinyl, Leather, and Paper journal September 2009
Highly Flexible and High-Performance Complementary Inverters of Large-Area Transition Metal Dichalcogenide Monolayers journal March 2016
Monolithic 3D CMOS Using Layered Semiconductors journal February 2016
Complementary Symmetry Silicon Nanowire Logic: Power‐Efficient Inverters with Gain journal August 2006
An innovative way of etching MoS2: Characterization and mechanistic investigation journal February 2013
Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach journal September 2008
High-Performance WSe 2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits journal July 2015
Low Power Consumption Complementary Inverters with n-MoS 2 and p-WSe 2 Dichalcogenide Nanosheets on Glass for Logic and Light-Emitting Diode Circuits journal September 2015
Static and Dynamic Performance of Complementary Inverters Based on Nanosheet α-MoTe 2 p -Channel and MoS 2 n -Channel Transistors journal December 2015
Air-Stable Surface Charge Transfer Doping of MoS 2 by Benzyl Viologen journal May 2014
Carbon Nanotube Transistor Arrays for Multistage Complementary Logic and Ring Oscillators journal September 2002
Doping-Free Fabrication of Carbon Nanotube Based Ballistic CMOS Devices and Circuits journal December 2007
How Good Can Monolayer MoS 2 Transistors Be? journal September 2011
III–V Complementary Metal–Oxide–Semiconductor Electronics on Silicon Substrates journal June 2012
High-Performance Single Layered WSe2 p-FETs with Chemically Doped Contacts journal June 2012
Integrated Circuits Based on Bilayer MoS2 Transistors journal January 2012
CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes journal January 2009
Top-Down Fabrication of Fully CMOS-Compatible Silicon Nanowire Arrays and Their Integration into CMOS Inverters on Plastic journal March 2011
High-Gain Inverters Based on WSe 2 Complementary Field-Effect Transistors journal April 2014
Phosphorene: An Unexplored 2D Semiconductor with a High Hole Mobility journal March 2014
Field-Effect Transistors Built from All Two-Dimensional Material Components journal May 2014
Almost Perfectly Symmetric SWCNT-Based CMOS Devices and Scaling journal October 2009
Dielectric Properties of MoS2 and Pt Catalysts: Effects of Temperature and Microwave Frequency journal December 2002
The chemistry of two-dimensional layered transition metal dichalcogenide nanosheets journal April 2013
High-mobility and low-power thin-film transistors based on multilayer MoS2 crystals journal January 2012
High-performance electronics using dense, perfectly aligned arrays of single-walled carbon nanotubes journal March 2007
Electronics and optoelectronics of two-dimensional transition metal dichalcogenides journal November 2012
Carbon nanotube field-effect inverters journal November 2001
Complementary metal oxide silicon integrated circuits incorporating monolithically integrated stretchable wavy interconnects journal July 2008
Carbon nanotube based ultra-low voltage integrated circuits: Scaling down to 0.4 V journal June 2012
Air stable n-doping of WSe2 by silicon nitride thin films with tunable fixed charge density journal August 2014
High gain, low noise, fully complementary logic inverter based on bi-layer WSe 2 field effect transistors journal August 2014
Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits journal November 2009
Phonons in single-layer and few-layer MoS 2 and WS 2 journal October 2011
Device scaling limits of Si MOSFETs and their application dependencies journal March 2001
One-gate-wide CMOS Inverter on laser-recrystallized polysilicon journal June 1980
A high density CMOS inverter with stacked transistors journal October 1981
Complementary Logic Gates and Ring Oscillators on Plastic Substrates by Use of Printed Ribbons of Single-Crystalline Silicon journal January 2008
Impact of Graphene Interface Quality on Contact Resistance and RF Device Performance journal August 2011
A Three-Dimensional Stacked Fin-CMOS Technology for High-Density ULSI Circuits journal September 2005
Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia journal January 2008
Process Technology Variation journal August 2011
Enhancement of adjustable threshold voltage range by substrate bias due to quantum confinement in ultrathin body SOI pMOSFETs journal December 2003
Heterogeneous Three-Dimensional Electronics by Use of Printed Semiconductor Nanomaterials journal December 2006
Stretchable and Foldable Silicon Integrated Circuits journal April 2008
Three-dimensional integrated circuits journal July 2006
A high-performance complementary inverter based on transition metal dichalcogenide field-effect transistors journal March 2015

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