Evaluating hardware architectures for real-time parallel algorithms using temporal specifications
This thesis presents techniques for expressing real-time parallel algorithms as Interval Temporal Logic (ITL) specifications. The language Tempura is used as a representation medium to permit specifications to be directly executed. Tempura is used to model the dependency relations within parallel algorithms. Models are presented for basic synchronization mechanisms including indivisible store operations, semaphores, message-passing primitives, and monitors. The operation of a simple multi-tasking executive is also described. ITL specifications are presented in the form of Tempura programs for a variety of hardware components. Methods are presented for modeling both combinational and sequential circuits. Composition and abstraction techniques are used to illustrate the development of architectural specifications. The formalism known as temporal projection is examined in conjunction with formal transformations as a method for mapping algorithm behavior to that of a target machine. To demonstrate the applicability of the proposed simulation method, a set of alternative hardware architectures are evaluated for real-time track correlation. Each machine employs a highly pipelined memory system based on high-speed VLSI building-block components.
- Research Organization:
- California Univ., Los Angeles, CA (USA)
- OSTI ID:
- 5213399
- Country of Publication:
- United States
- Language:
- English
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