An analysis of architectures for high-performance transaction processing
A detailed queueing network simulation model has been constructed for each of the architectures. Chapter 2 describes the simulation models for the three architectures in terms of their components: the hardware machine architectures, the software system, the workload, the model of intra-transaction parallelism, the concurrency control algorithm, the buffer cache model and the logging model. Numerous alternative algorithms exist for locking and buffer consistency protocols for the Shared Disks architecture. Chapter 3 of this thesis examines four promising locking protocols to determine the best one. Two methods are studied for reducing the message overheads of these protocols. Chapter 4 presents a study of how lock contention varies in each architecture as different workload parameters are changed. Lock contention is determined by five workload parameters. Each parameter is studied in a separate experiment by varying it over a reasonable range while holding other parameters constant. Chapter 5 studies the effects of intra-transaction parallelism on performance in the three architectures. Three different types of workloads are considered and the differences they cause in the performance of parallelism are pointed out. Chapter 6 presents a collection of miscellaneous experiments which measure sensitivity to message costs, effect of unbalanced workloads, the effect of increasing buffer space and tradeoffs between partitioned and sequential file systems.
- Research Organization:
- California Univ., Berkeley, CA (USA)
- OSTI ID:
- 6037723
- Country of Publication:
- United States
- Language:
- English
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