Algorithms suitable for VLSI implementation

Thesis/Dissertation · Wed Jan 01 04:00:00 EST 1986

OSTI ID:5152021

Neaderhouser, C E

Design and analysis of algorithms implementable in VLSI (very large scale integration) are studied. In particular, algorithms for the fundamental process of multiplication and division of integers and for finding the greatest common divisor of two integers are examined. A design for a fast multiplier for 54-bit integers, implemented on a commercially available chip, is presented. The design is also analyzed for its performance for general n, and it is shown that, theoretically at least, the design achieves the best possible time for multiplication, O(log n). With respect to division, a binary algorithm is developed, and it is shown that the algorithm can be implemented in a systolic array of simple cells in the best possible area (area O(N) for n-bit inputs). A cellular-array implementation of this algorithm is also described. For the greatest common divisor problem, it is shown that, under reasonable design assumptions, any chip that finds the greatest common divisor of two n-bit integers must have area A and time T satisfying AT/sup 2..cap alpha../ = OMEGA (n/sup 1 + ..cap alpha../) for O less than or equal to ..cap alpha.. less than or equal to 1. The proof of this result is the first to use the concept of multiple information-flow barriers

• Research Organization: Texas A and M Univ., College Station (USA)
• OSTI ID: 5152021
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ALGORITHMS
COMPUTER CALCULATIONS
DESIGN
ELECTRONIC CIRCUITS
IMPLEMENTATION
INTEGRATED CIRCUITS
MATHEMATICAL LOGIC
MICROELECTRONIC CIRCUITS