VLSI binary multiplier using residue number systems
Conference
·
OSTI ID:5303029
The idea of performing multiplication of n-bit binary numbers using a hardware based on residue number systems is considered. This paper develops the design of a VLSI chip deriving area and time upper bounds of a n-bit multiplier. To perform multiplication using residue arithmetic, numbers are converted from binary to residue representation and, after residue multiplication, the result is reconverted to the original notation. It is shown that the proposed design requires an area a=o(n/sup 2/ log n) and an execution time t=o(log/sup 2/n). 7 references.
- OSTI ID:
- 5303029
- Report Number(s):
- CONF-820908-
- Country of Publication:
- United States
- Language:
- English
Similar Records
Design and performance of VLSI based parallel multiplier
Algorithms suitable for VLSI implementation
Design and clocking of VLSI multipliers
Conference
·
Fri Dec 31 23:00:00 EST 1982
·
OSTI ID:5257882
Algorithms suitable for VLSI implementation
Thesis/Dissertation
·
Tue Dec 31 23:00:00 EST 1985
·
OSTI ID:5152021
Design and clocking of VLSI multipliers
Thesis/Dissertation
·
Sun Dec 31 23:00:00 EST 1989
·
OSTI ID:6054460