VLSI architectures for multidimensional Fourier transform processing

Journal Article · Sat Oct 31 23:00:00 EST 1987 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/TC.1987.5009467· OSTI ID:5756745

Gertner, I; Shamash, M

It is often desirable in modern signal processing applications to perform two-dimensional or three-dimensional Fourier transforms. Until the advent of VLSI it was not possible to think about one chip implementation of such processes. In this paper several methods for implementing the multidimensional Fourier transform together with the VLSI computational model are reviewed and discussed. The authors show that the lower bound for the computation of the multidimensional transform is O(n/sup 2/ log/sup 2/ n). Existing nonoptimal architectures suitable for implementing the 2-D transform, the RAM array transposer, mesh connected systolic array, and the linear systolic matrix vector multiplier are discussed for area time tradeoff.

• Research Organization: Dept. of Electrical Engineering, Technion-Israel Institute of Technology, Haifa 32000
• OSTI ID: 5756745
• Journal Information: IEEE Trans. Comput.; (United States), Journal Name: IEEE Trans. Comput.; (United States) Vol. C-36:11; ISSN ITCOB
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTERIZED SIMULATION
DOCUMENT TYPES
ELECTRONIC CIRCUITS
FOURIER TRANSFORMATION
INTEGRAL TRANSFORMATIONS
INTEGRATED CIRCUITS
MICROELECTRONIC CIRCUITS
ONE-DIMENSIONAL CALCULATIONS
PARALLEL PROCESSING
PROGRAMMING
REVIEWS
SIGNAL CONDITIONING
SIMULATION
THREE-DIMENSIONAL CALCULATIONS
TRANSFORMATIONS
TWO-DIMENSIONAL CALCULATIONS
VECTOR PROCESSING