A reconfigurable fully parallel associative processor

Journal Article · Tue Jan 31 23:00:00 EST 1989 · Journal of Parallel and Distributed Computing; (USA)

DOI:https://doi.org/10.1016/0743-7315(89)90043-9· OSTI ID:5145355

Scherson, I D; Ilgen, S ^[1]

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1. California Univ., Santa Barbara, CA (USA). Dept. of Electrical and Computer Engineering

An associative parallel processing system using novel VLSI associative memory is described. By optimizing the VLSI associative memory architecture, the restrictions that are generally ascribed to classical associative memory systems no longer exist. High performance is achieved without sacrificing memory density due to enhancements in the peripheral circuitry rather than in the storage cell. Using the chip as a basic building block, a dynamically reconfigurable associative processor is proposed. A shifter interconnection network provides the interchip communication required to emulate different networks with a constant routing time for processor data transfers. It also allows for fast communication with a host computer. Parallel arithmetic algorithms are given, together with the application of the Associative Processor to diverse areas such as computer graphics, image processing, and list processing. Results are summarized to show the power of the proposed associative machine which proves to be a general-purpose parallel processor with a broad range of applications.

• OSTI ID: 5145355
• Journal Information: Journal of Parallel and Distributed Computing; (USA), Journal Name: Journal of Parallel and Distributed Computing; (USA) Vol. 6:1; ISSN JPDCE; ISSN 0743-7315
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ARRAY PROCESSORS
COMPUTER ARCHITECTURE
COMPUTER GRAPHICS
ELECTRONIC CIRCUITS
IMAGE PROCESSING
INTEGRATED CIRCUITS
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
OPTIMIZATION
PARALLEL PROCESSING
PERFORMANCE
PROCESSING
PROGRAMMING