Pringle: a test bed for parallel computer and parallel I/O architectures

Thesis/Dissertation · Tue Jan 01 04:00:00 EST 1985

OSTI ID:5378520

Kapauan, A A

The design and implementation of a multiple instruction stream, multiple data stream message-passing parallel computer called Pringle is described. Pringle was originally constructed to be a hardware emulator for the CHiP or Configurable, Highly Parallel computer. It consists of an ensemble of 64 identical processing elements, and 32 I/O processing elements. Each processing element is based on the Intel 8031 microprocessor chip and contain a small amount of read-write memory. Communication between processing elements is implemented using a high speed bus that emulates a reconfigurable point to point message passing network. It is shown that a multiple microprocessor parallel computer such as Pringle can be utilized effectively in the development of parallel computer algorithms. Its reconfigurable interconnection network allows researchers to experiment with various network topologies. The problem of designing an adequate I/O system for Pringle in particular and moderately fine grain ensemble machines in general is addressed. It is shown that for machines of this class, the I/O system must exhibit both a multiplicity of dedicated I/O processors and some degree of symmetry in the accessibility of these processors. The Pringle I/O system is presented as one solution to this problem.

• Research Organization: Purdue Univ., Lafayette, IN (USA)
• OSTI ID: 5378520
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS
990200* -- Mathematics & Computers
ALGORITHMS
COMPUTER ARCHITECTURE
COMPUTER NETWORKS
COMPUTERS
DIGITAL COMPUTERS
ELECTRONIC CIRCUITS
MATHEMATICAL LOGIC
MATHEMATICS
MICROELECTRONIC CIRCUITS
MICROPROCESSORS
PARALLEL PROCESSING
PROGRAMMING
SUPERCOMPUTERS
TOPOLOGY