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Timing and area optimization of CMOS combinational-logic circuits accounting for total-dose radiation effects

Conference · · IEEE Trans. Nucl. Sci.; (United States)
OSTI ID:5131214
An algorithm for optimizing CMOS VLSI combinational logic circuits for operation in total-dose environments is presented. The width-to-length ratios of the MOS transistors are determined which allow the circuit to meet specified timing requirements while minimizing circuit area. The logic circuit is modeled by an equivalent resistor-capacitor (RC) network, where the resistors and capacitors are functions of transistor width-to-length ratios. The total-dose radiation dependence is modeled as a variation in the resistors. The algorithm has been implemented and tested on example circuits, and the results have been verified using SPICE.
Research Organization:
Dept. of Electrical and Computer Engineering, Box 7911, North Carolina State Univ., Raleigh, NC 27695-7911 (US)
OSTI ID:
5131214
Report Number(s):
CONF-8707112-
Conference Information:
Journal Name: IEEE Trans. Nucl. Sci.; (United States) Journal Volume: NS-34:6
Country of Publication:
United States
Language:
English