A methodology for the identification of worst-case test vectors for logical faults induced in CMOS circuits by total dose

Journal Article · Thu Dec 01 04:00:00 EST 1994 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.340619· OSTI ID:32033

Abou-Auf, A A; Eisen, H A ^[1]; Barbe, D F ^[2]

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1. Army Research Lab., Adelphi, MD (United States)
2. Univ. of Maryland, College Park, MD (United States). Electrical Engineering Dept.

A new methodology was developed for the identification of the worst-case combination of irradiation and postirradiation test vectors. The methodology significantly simplifies total-dose testing of CMOS VLSI devices. It also provides more accurate assessment of failure levels for such devices.

• OSTI ID: 32033
• Report Number(s): CONF-940726--
• Journal Information: IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6Pt1 Vol. 41; ISSN IETNAE; ISSN 0018-9499
• Country of Publication: United States
• Language: English

Related Subjects

44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
ANALYTICAL SOLUTION
COMPUTERIZED SIMULATION
FAILURES
INTEGRATED CIRCUITS
MATHEMATICAL MODELS
PERFORMANCE TESTING
PHYSICAL RADIATION EFFECTS