Gate-level modeling of leakage current failure induced by total dose for the generation of worst-case test vectors

Journal Article · Sun Dec 01 04:00:00 EST 1996 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.556924· OSTI ID:445495

Abou-Auf, A A ^[1]

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1. Army Research Lab., Adelphi, MD (United States)

The total-dose testing standard, MIL-STD-883, method 1019, emphasizes the use of worst-case test vectors whenever possible. Despite this emphasis, worst-case test vectors are not typically used in total-dose testing, because the technology of generating worst-case test vectors has not yet matured. The authors have recently developed a practical methodology to easily identify worst-case test vectors for logical faults induced in CMOS combinatorial circuits by total dose. Here, a novel gate-level model has been developed for the automatic generation of worst-case test vectors for leakage current failure induced in CMOS devices by total dose.

• OSTI ID: 445495
• Report Number(s): CONF-960773--
• Journal Information: IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6Pt1 Vol. 43; ISSN IETNAE; ISSN 0018-9499
• Country of Publication: United States
• Language: English

Related Subjects

44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
FAILURES
LEAKAGE CURRENT
LOGIC CIRCUITS
MATHEMATICAL MODELS
PHYSICAL RADIATION EFFECTS
RADIATION DOSES
TESTING