Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack
Journal Article
·
· Journal of Materials Research
- Department of Materials and Nuclear Engineering, University of Maryland, College Park, Maryland 20742 (United States)
- Surface Modification Branch, U.S. Naval Research Laboratory, Washington, DC 20375 (United States)
- Army Research Laboratories, Adelphi, Maryland 20783 (United States)
Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructures were grown by pulsed laser deposition using a composite conducting barrier layer of Pt/TiN on poly-Si/Si substrate. The growth of the ferroelectric heterostructure is accomplished at a temperature in the range of 500{endash}600{degree}C. This integration results in a 3-dimensional stacked capacitor-transistor geometry which is important for high density nonvolatile memory (HDNVM) applications. Transmission electron microscopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion. The ferroelectric properties and reliability of these integrated capacitors were studied extensively at room temperature and 100{degree}C for different growth temperatures. The capacitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applications. {copyright} {ital 1997 Materials Research Society.}
- OSTI ID:
- 508984
- Journal Information:
- Journal of Materials Research, Journal Name: Journal of Materials Research Journal Issue: 6 Vol. 12; ISSN JMREEE; ISSN 0884-2914
- Country of Publication:
- United States
- Language:
- English
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