Radiation hardening of MOS integrated circuits on <111> silicon
Effective procedures have been developed for hardening MOS transistors by minimizing radiation-induced threshold-voltage shifts in the SiO$sub 2$ gate insulator. These existing procedures were developed primarily for [100] oriented silicon. The radiation-hardening work reported herein was based upon specific requirements for use of [111] oriented silicon. The objective of this study was to evaluate the effectiveness of existing gate-insulator radiation-hardening procedures when applied to PMOS integrated circuits fabricated on [111] bulk silicon substrates. These procedures were proven effective in hardening [111] PMOS integrated circuits. However, there remains a significant difference between the radiation hardness of [111] and [100] PMOS integrated circuits. (auth)
- Research Organization:
- Rockwell International, Anaheim, CA
- NSA Number:
- NSA-33-020347
- OSTI ID:
- 4087858
- Journal Information:
- IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2190-2192, Journal Name: IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2190-2192; ISSN IETNA
- Country of Publication:
- United States
- Language:
- English
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