Development and integration of applique decoupling capacitors

Conference · Tue Oct 01 04:00:00 EDT 1996

OSTI ID:378849

Garino, T J; Dimos, D; Lockwood, S J

For high-speed integrated circuit applications, it is important to interconnect decoupling capacitors and integrated circuits (ICs) as intimately as possible, to minimize parasitic impedances. This can be achieved by mounting free-standing, thin film capacitors directly onto ICs as part of a chip-scale packaging approach. These applique capacitors utilize a chemically-prepared PLZT dielectric, which is nominally 1 {micro}m thick. The small size and weight of applique capacitors can be used to improve packaging efficiency. Applique capacitors, which are initially fabricated on silicon wafers, have high permittivity ({var_epsilon} {approx_equal} 1,000), low loss (tan{delta} {approx_equal} 0.01) and high breakdown strength (E{sub b} {approx_equal} 1 MV/cm) and leakage resistance ({rho} > 10{sup 14} {Omega}-cm {at} 125 C). Various processes being developed to remove the capacitors from the silicon substrate and reattach them to ICs is described. In addition, a concept for interconnecting the capacitors using a repatterning process is discussed.

• Research Organization: Los Alamos National Lab., NM (United States)
• Sponsoring Organization: USDOE, Washington, DC (United States)
• DOE Contract Number: AC04-94AL85000
• OSTI ID: 378849
• Report Number(s): SAND--96-2153C; CONF-960894--3; ON: DE96014497
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
CAPACITORS
FABRICATION
FREQUENCY DEPENDENCE
IMPEDANCE
INTEGRATED CIRCUITS
PERFORMANCE