A time digitizer CMOS gate-array with a 250 ps time resolution

Journal Article · Thu Feb 01 04:00:00 EST 1996 · IEEE Journal of Solid-State Circuits

DOI:https://doi.org/10.1109/4.487998· OSTI ID:231102

Arai, Yasuo ^[1]

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1. National Lab. for High Energy Physics, Tsukuba, Ibaraki (Japan)

Recent high-energy physics experiments are demanding a pipeline (deadtime-less) time-to-digital converter (TDC) with a time resolution of better than 500 ps and a double-pulse resolution of less than 30 ns. The TDC must keep all of the timing history until a trigger signal arrives about 3 {micro}s later. In large experiments, since the number of channels used is more than 100 k, the device must have a low power dissipation, a high circuit density and a low cost. A pipelined time digitizer CMOS gate-array has been developed using 0.5 {micro}m Sea-of-Gate technology. Precise timing signals which are used to sample input signals are generated from 32 taps of an asymmetric ring oscillator. The frequency of the oscillator is controlled by a phase-locked loop (PLL) circuit which runs in the 10--50 MHz frequency range. A test chip has been developed and tested; a time resolution of 250 ps rms at 40 MHz clock was measured. The chip has 4 channels and encoding circuits for both the rising and the falling edges of the input signals. The chip has 128-word dual-port memories, allowing the histories of the input signals to be stored and causing no deadtime for the conversion.

• OSTI ID: 231102
• Journal Information: IEEE Journal of Solid-State Circuits, Journal Name: IEEE Journal of Solid-State Circuits Journal Issue: 2 Vol. 31; ISSN IJSCBC; ISSN 0018-9200
• Country of Publication: United States
• Language: English

Related Subjects

44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
DESIGN
DIGITIZERS
INTEGRATED CIRCUITS
PERFORMANCE
PERFORMANCE TESTING
RADIATION DETECTORS
TIMING CIRCUITS