An integrated CMOS 0.15 ns digital timing generator for TDC`s and clock distribution systems
- CERN, Geneva (Switzerland)
This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time to Digital Converters (TDC) and clock alignment functions. The timing generator is implemented as an array of locked loops. This architecture enables a timing generator with sub-gate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing-generator has been mapped into a 1.0 {micro}m CMOS process a RMS error of the time taps of 48 ps has been measured with a bin size 0.15 ns. Used as a TDC device a RMS error of {minus}6 ps has been obtained. A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives.
- OSTI ID:
- 136898
- Report Number(s):
- CONF-941061--
- Journal Information:
- IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 4Pt1 Vol. 42; ISSN 0018-9499; ISSN IETNAE
- Country of Publication:
- United States
- Language:
- English
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