Elimination of charge-enhancement effects in GaAs FETs with a low-temperature grown GaAs buffer layer

Journal Article · Thu Nov 30 23:00:00 EST 1995 · IEEE Transactions on Nuclear Science

DOI:https://doi.org/10.1109/23.488787· OSTI ID:203705

McMorrow, D; Weatherford, T R; Curtice, W R; Knudson, A R; Buchner, S; Melinger, J S; Tran, L H; Campbell, A B ^[1]

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1. Naval Research Lab., Washington, DC (United States)

The use of low temperature grown GaAs (LT GaAs) buffer layer in GaAs FETs is shown via computer simulation and experimental measurement to reduce ion-induced charge collection by two to three orders of magnitude. This reduction in collected charge is associated with the efficient reduction of charge-enhancement mechanisms in the FETs. Error rate calculations indicate that the soft error rate of LT GaAs integrated circuits will be reduced by several orders of magnitude when compared to conventional FET-based GaAs ICs.

• OSTI ID: 203705
• Report Number(s): CONF-950716--
• Journal Information: IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6Pt1 Vol. 42; ISSN 0018-9499; ISSN IETNAE
• Country of Publication: United States
• Language: English

Related Subjects

44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
CHARGE COLLECTION
COMPUTERIZED SIMULATION
FIELD EFFECT TRANSISTORS
GALLIUM ARSENIDES
HEAVY IONS
INTEGRATED CIRCUITS
PHYSICAL RADIATION EFFECTS
SPACE FLIGHT
THEORETICAL DATA