Critical charge concepts for CMOS SRAMs
- Sandia National Labs., Albuquerque, NM (United States)
The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge can be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must taken into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.
- Research Organization:
- Sandia National Laboratory
- DOE Contract Number:
- AC04-94AL85000
- OSTI ID:
- 203700
- Report Number(s):
- CONF-950716--
- Journal Information:
- IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6Pt1 Vol. 42; ISSN 0018-9499; ISSN IETNAE
- Country of Publication:
- United States
- Language:
- English
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