Prioritizing local and remote memory access in a non-uniform memory access architecture
A miss in a cache by a thread in a wavefront is detected. The wavefront includes a plurality of threads that are executing a memory access request concurrently on a corresponding plurality of processor cores. A priority is assigned to the thread based on whether the memory access request is addressed to a local memory or a remote memory. The memory access request for the thread is performed based on the priority. In some cases, the cache is selectively bypassed depending on whether the memory access request is addressed to the local or remote memory. A cache block is requested in response to the miss. The cache block is biased towards a least recently used position in response to requesting the cache block from the local memory and towards a most recently used position in response to requesting the cache block from the remote memory.
- Research Organization:
- Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- AC52-07NA27344; B620717
- Assignee:
- Advanced Micro Devices, Inc. (Santa Clara, CA)
- Patent Number(s):
- 10,838,864
- Application Number:
- 15/992,885
- OSTI ID:
- 1771644
- Resource Relation:
- Patent File Date: 05/30/2018
- Country of Publication:
- United States
- Language:
- English
Instruction and Logic for Adaptive Dataset Priorities in Processor Caches
|
patent-application | March 2016 |
Cache Entry Replacement Based on Penalty of Memory Access
|
patent-application | April 2018 |
Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance
|
conference | October 2015 |
Cache prefetching from non-uniform memories
|
patent | December 2013 |
Similar Records
Virtual cache system using page level number generating cam to access other memories for processing requests relating to a page
Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests