Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests
Abstract
A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.
- Inventors:
- Publication Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1156946
- Patent Number(s):
- 8,832,415
- Application Number:
- 12/984,329
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Gala, Alan, and Ohmacht, Martin. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests. United States: N. p., 2014.
Web.
Gala, Alan, & Ohmacht, Martin. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests. United States.
Gala, Alan, and Ohmacht, Martin. Tue .
"Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests". United States. https://www.osti.gov/servlets/purl/1156946.
@article{osti_1156946,
title = {Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests},
author = {Gala, Alan and Ohmacht, Martin},
abstractNote = {A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.},
doi = {},
url = {https://www.osti.gov/biblio/1156946},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {9}
}
Works referenced in this record:
Multi-thread packet processor
patent-application, June 2002
- Modelski, Richard P.; Craren, Michael J.
- US Patent Application 09/741857; 20020083297
Cache way prediction based on instruction base register
patent-application, September 2002
- Van De Waerdt, Jan-Wiliem; Stravers, Paul
- US Patent Application 09/805384; 20020133672
Fast and accurate cache way selection
patent-application, January 2003
- van de Waerdt, Jan-Willem
- US Patent Application 09/887463; 20030014597
Stall technique to facilitate atomicity in processor execution of helper set
patent-application, September 2004
- Thimmannagari, Chandra M. R.; Iacobovici, Sorin; Sugumar, Rabin A.
- US Patent Application 10/395417; 20040193845
Synchronization of parallel processes
patent-application, September 2005
- Saha09/15/2005, Bratin
- US Patent Application 10/797886; 20050204119
Processor with cache way prediction and method thereof
patent-application, May 2006
- Park, Gi-ho; Lee, Hoi-jin
- US Patent Application 11/264158; 20060095680
Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache
patent-application, June 2006
- Kottapalli, Sailesh
- US Patent Application 11/026316; 20060143390
Transaction based shared data operations in a multiprocessor environment
patent-application, July 2006
- Kottapalli, Sailesh; Crawford, John H.; Vaid, Kushagra
- US Patent Application 11/027623; 20060161740
Implementation of load linked and store conditional operations
patent-application, July 2006
- Onufryk, Peter Z.; Stichter, Allen
- US Patent Application 11/021894; 20060161919
Apparatus and method for sparse line write transactions
patent-application, February 2007
- Gaskins, Darius D.
- US Patent Application 11/364704; 20070028021
Thread-Shared Software Code Caches
patent-application, March 2007
- Bruening, Derek L.; Kiriansky, Vladimir L.; Garnett, Tim
- US Patent Application 11/533712; 20070067573
Separate data/coherency caches in a shared memory multiprocessor system
patent-application, July 2007
- Hutton, David S.; Jackson, Kathryn M.; Langston, Keith N.
- US Patent Application 11/334280; 20070168619
Architectural support for thread level speculative execution
patent-application, August 2007
- Gara, Alan G.; Salapura, VAlentina
- US Patent Application 11/351829; 20070192540
Snoop Filter Directory Mechanism in Coherency Shared Memory System
patent-application, December 2007
- Hoover, Russell D.; Mejdrich, Eric O.; Kriegel, Jon K.
- US Patent Application 11/848960; 20070294481
Prefetch Miss Indicator for Cache Coherence Directory Misses on External Caches
patent-application, August 2008
- Lais, Eric N.; Desota, Donald R.; Joersz, Rob
- US Patent Application 12/105405; 20080195820
Method and Apparatus for Context Switching and Synchronization
patent-application, October 2008
- Kriegel, Jon K.; Mejdrich, Eric Oliver
- US Patent Application 11/736936; 20080263339
Method, Apparatus, System and Program Product Supporting Improved Access Latency for a Sectored Directory
patent-application, December 2008
- Averill, Duane Arlyn; Skarphol, Jonathan C.; Vanderpool, Brian T.
- US Patent Application 11/758851; 20080307169
Method and Apparatus for Employing Multi-Bit Register File Cells and SMT Thread Groups
patent-application, December 2008
- Gschwind, Michael
- US Patent Application 11/762137; 20080313437
System and Method for Executing Nested Atomic Blocks Using Split Hardware Transactions
patent-application, January 2009
- Lev, Yosef; Maessen, Jan-Willem
- US Patent Application 11/840439; 20090031310
Enabling Speculative State Information in a Cache Coherency Protocol
patent-application, March 2009
- Madriles Gimeno, Carlos; Garcia Quinones, Carlos; Marcuello, Pedro
- US Patent Application 12/226793; 20090083488
Efficient Deterministic Multiprocessing
patent-application, September 2009
- Ceze, Luis; Oskin, Mark H.; Devietti, Joseph Luke
- US Patent Application 12/402395; 20090235262
Early header CRC in data response packets with variable gap count
patent-application, October 2009
- Allison, Brian D.; Barrett, Wayne M.; Rudquist, MArk L.
- US Patent Application 12/108637; 20090268736
Method, System and Apparatus for Reducing Memory Traffic in a Distributed Memory System
patent-application, November 2009
- Moga, Adrian; Agarwal, Rajat; Mandviwalla, Malcolm
- US Patent Application 12/113268; 20090276581
Cache control device and control method
patent-application, July 2010
- Kiyota, Naohiro
- US Patent Application 12/654376; 20100169577
Using Time Stamps to Facilitate Load Reordering
patent-application, August 2010
- Cypher, Robert. E.
- US Patent Application 12/369426; 20100205609
Multi-Domain Management of a Cache in a Processor System
patent-application, September 2010
- Bouvier, Daniel
- US Patent Application 12/419139; 20100235580
Using Domains for Physical Address Management in a Multiprocessor System
patent-application, September 2010
- Bouvier, Daniel L.
- US Patent Application 12/402345; 20100235598
Hierarchical Bloom Filters for Facilitating Concurrency Control
patent-application, December 2010
- Cypher, Robert E.
- US Patent Application 12/493523; 20100332765
Store Aware Prefetching for a Datastream
patent-application, March 2011
- Sander, Benjamin T.; Swamy, Bharath Narasimha; Punyamurtula, Swamy
- US Patent Application 12/558465; 20110066811
Cache Spill Management Techniques
patent-application, June 2011
- Steely, JR., Simon C.; Hasenplaugh, William C.; Jaleel, Aamer
- US Patent Application 12/639214; 20110145501
Pre-Fetching for a Sibling Cache
patent-application, September 2011
- Karlsson, Martin R.; Chaudhry, Shailender; Cypher, Robert E.
- US Patent Application 12/724639; 20110231612