Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests
Abstract
A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.
- Inventors:
- Publication Date:
- Research Org.:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Org.:
- USDOE
- OSTI Identifier:
- 1156946
- Patent Number(s):
- 8,832,415
- Application Number:
- 12/984,329
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- DOE Contract Number:
- B554331
- Resource Type:
- Patent
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 97 MATHEMATICS AND COMPUTING
Citation Formats
Gala, Alan, and Ohmacht, Martin. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests. United States: N. p., 2014.
Web.
Gala, Alan, & Ohmacht, Martin. Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests. United States.
Gala, Alan, and Ohmacht, Martin. Tue .
"Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests". United States. https://www.osti.gov/servlets/purl/1156946.
@article{osti_1156946,
title = {Mapping virtual addresses to different physical addresses for value disambiguation for thread memory access requests},
author = {Gala, Alan and Ohmacht, Martin},
abstractNote = {A multiprocessor system includes nodes. Each node includes a data path that includes a core, a TLB, and a first level cache implementing disambiguation. The system also includes at least one second level cache and a main memory. For thread memory access requests, the core uses an address associated with an instruction format of the core. The first level cache uses an address format related to the size of the main memory plus an offset corresponding to hardware thread meta data. The second level cache uses a physical main memory address plus software thread meta data to store the memory access request. The second level cache accesses the main memory using the physical address with neither the offset nor the thread meta data after resolving speculation. In short, this system includes mapping of a virtual address to a different physical addresses for value disambiguation for different threads.},
doi = {},
url = {https://www.osti.gov/biblio/1156946},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {9}
}