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DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Journal Article · · IEEE Transactions on Nuclear Science
 [1];  [1];  [1];  [1];  [1];  [1];  [1];  [1];  [2];  [2];  [2];  [2]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
  2. Vanderbilt Univ., Nashville, TN (United States)
+ Show Author Affiliations
Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.
Research Organization:
Sandia National Laboratories (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE National Nuclear Security Administration (NNSA)
Grant/Contract Number:
AC04-94AL85000; NA0003525
OSTI ID:
1619211
Alternate ID(s):
OSTI ID: 1641057
Report Number(s):
SAND--2019-7719J; 677143
Journal Information:
IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6 Vol. 67; ISSN 0018-9499
Publisher:
IEEECopyright Statement
Country of Publication:
United States
Language:
English

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Related Subjects

42 ENGINEERING
Implants
Ions
Layout
Logic gates
MOSFET
Radiation hardening by design (RHBD)
Silicon
sequential circuits
single-event upset (SEU)
transmission gates