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Charge collection in submicron CMOS/SOI technology

Journal Article · · IEEE Transactions on Nuclear Science
DOI:https://doi.org/10.1109/23.659027· OSTI ID:644205
;  [1];  [2];  [3]; ;  [4]; ;  [5]
  1. CEA, Bruyeres-le-Chatel (France)
  2. Naval Research Lab., Washington, DC (United States)
  3. SFA, Landover, MD (United States)
  4. ICI, McLean, VA (United States)
  5. CEA-LETI, Grenoble (France)
+ Show Author Affiliations

The authors present experimental measurements of charge collection spectroscopy from high energy ion strikes in submicron CMOS/SOI devices. Due to the specific structure of SOI technology, with symmetrical source and drain junctions, a direct equivalence between upset mechanism and charge collection is established. The bipolar mechanism, responsible for the amplification of the deposited charge is discussed based on 2D device simulations. Based on the experimental data the authors determine qualitatively the influence of transistor geometry on the bipolar gain. Finally the limits of the usual SEU concepts (LET threshold and cross section) are discussed for scaled devices.

OSTI ID:
644205
Report Number(s):
CONF-970711--
Journal Information:
IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 6Pt1 Vol. 44; ISSN 0018-9499; ISSN IETNAE
Country of Publication:
United States
Language:
English

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Related Subjects

44 INSTRUMENTATION
INCLUDING NUCLEAR AND PARTICLE DETECTORS
CHARGE COLLECTION
FAILURES
IONS
PHYSICAL RADIATION EFFECTS
SEMICONDUCTOR DEVICES