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Title: Memory address translation

Patent ·
OSTI ID:1600328
; ;

A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

Research Organization:
Arm Limited, Cambridge (United Kingdom)
Sponsoring Organization:
USDOE
Assignee:
ARM Limited (Cambridge, GB)
Patent Number(s):
10,489,304
Application Number:
15/650,056
OSTI ID:
1600328
Resource Relation:
Patent File Date: 07/14/2017
Country of Publication:
United States
Language:
English

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