Memory system for a data processing network
A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.
- Research Organization:
- Arm Ltd., Cambridge (United States)
- Sponsoring Organization:
- USDOE
- Assignee:
- Arm Limited (Cambridge, GB)
- Patent Number(s):
- 10,534,719
- Application Number:
- 15/819,328
- OSTI ID:
- 1632438
- Country of Publication:
- United States
- Language:
- English
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