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Title: Optimizing TLB entries for mixed page size storage in contiguous memory

Patent ·
OSTI ID:1083581
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A system and method for accessing memory are provided. The system comprises a lookup buffer for storing one or more page table entries, wherein each of the one or more page table entries comprises at least a virtual page number and a physical page number; a logic circuit for receiving a virtual address from said processor, said logic circuit for matching the virtual address to the virtual page number in one of the page table entries to select the physical page number in the same page table entry, said page table entry having one or more bits set to exclude a memory range from a page.

Research Organization:
International Business Machines Corp., Armonk, NY (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
B554331
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,429,377
Application Number:
12/684,642
OSTI ID:
1083581
Country of Publication:
United States
Language:
English

References (14)

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Optimization of All-to-All Communication on the Blue Gene/L Supercomputer conference September 2008
Multi-Petascale Highly Efficient Parallel Supercomputer patent-application September 2011
Computer memory address control apparatus utilizing hashed address tags in page tables which are compared to a combined address tag and index which are longer than the basic data width of the associated computer patent March 1998
Optimized scalable network switch patent December 2007
System and Method for Cache-Locking Mechanism Using Translation Table Attributes for Replacement Class ID Determination patent-application January 2009
Three input variable subfield comparation for fast matching patent March 2005
Concurrent page tables patent May 2001

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