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Title: Mechanism for reducing page migration overhead in memory systems

Abstract

A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.

Inventors:
; ;
Publication Date:
Research Org.:
Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1568554
Patent Number(s):
10,339,067
Application Number:
15/626,623
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
DOE Contract Number:  
AC52-07NA27344; B609201
Resource Type:
Patent
Resource Relation:
Patent File Date: 06/19/2017
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Eckert, Yasuko, Vijayaraghavan, Thiruvengadam, and Loh, Gabriel H. Mechanism for reducing page migration overhead in memory systems. United States: N. p., 2019. Web.
Eckert, Yasuko, Vijayaraghavan, Thiruvengadam, & Loh, Gabriel H. Mechanism for reducing page migration overhead in memory systems. United States.
Eckert, Yasuko, Vijayaraghavan, Thiruvengadam, and Loh, Gabriel H. Tue . "Mechanism for reducing page migration overhead in memory systems". United States. https://www.osti.gov/servlets/purl/1568554.
@article{osti_1568554,
title = {Mechanism for reducing page migration overhead in memory systems},
author = {Eckert, Yasuko and Vijayaraghavan, Thiruvengadam and Loh, Gabriel H.},
abstractNote = {A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.},
doi = {},
url = {https://www.osti.gov/biblio/1568554}, journal = {},
number = ,
volume = ,
place = {United States},
year = {2019},
month = {7}
}

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