Mechanism for reducing page migration overhead in memory systems

Patent · Tue Jul 02 00:00:00 EDT 2019

OSTI ID:1568554

Eckert, Yasuko; Vijayaraghavan, Thiruvengadam; Loh, Gabriel H.

A technique for use in a memory system includes swapping a first plurality of pages of a first memory of the memory system with a second plurality of pages of a second memory of the memory system. The first memory has a first latency and the second memory has a second latency. The first latency is less than the second latency. The technique includes updating a page table and triggering a translation lookaside buffer shootdown to associate a virtual address of each of the first plurality of pages with a corresponding physical address in the second memory and to associate a virtual address for each of the second plurality of pages with a corresponding physical address in the first memory.

• Research Organization: Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
• Sponsoring Organization: USDOE
• DOE Contract Number: AC52-07NA27344; B609201
• Assignee: Advanced Micro Devices, Inc. (Santa Clara, CA)
• Patent Number(s): 10,339,067
• Application Number: 15/626,623
• OSTI ID: 1568554
• Resource Relation: Patent File Date: 06/19/2017
• Country of Publication: United States
• Language: English

Related Subjects

97 MATHEMATICS AND COMPUTING