Memory node controller
A memory node controller for a node of a data processing network, the network including at least one computing device and at least one data resource, each data resource addressed by a physical address. The node is configured to couple the at least one computing device with the at least one data resource. Elements of the data processing network are addressed via a system address space. The memory node controller includes a first interface to the at least one data resource, a second interface to the at least one computing device, and a system to physical address translator cache configured to translate a system address in the system address space to a physical address in the physical address space of the at least one data resource.
- Research Organization:
- ARM Limited, Cambridge (United Kingdom)
- Sponsoring Organization:
- USDOE
- Assignee:
- ARM Limited (Cambridge, GB)
- Patent Number(s):
- 10,467,159
- Application Number:
- 15/650,008
- OSTI ID:
- 1600250
- Country of Publication:
- United States
- Language:
- English
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