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Title: Per-page control of physical address space distribution among memory modules

Patent ·
OSTI ID:1568306
; ;

Systems, apparatuses, and methods for implementing per-page control of physical address space distribution among memory modules are disclosed. A computing system includes a plurality of processing units coupled to a plurality of memory modules. A determination is made as to which physical address space distribution granularity to implement for physical memory pages allocated for a first data structure. The determination can be made on a per-data-structure basis (e.g., file, page, block, etc.) or on a per-application-basis. A physical address space distribution granularity is encoded as a property of each physical memory page allocated for the first data structure, and physical memory pages of the first data structure distributed across the plurality of memory modules based on a selected physical address space distribution granularity. Page table entries (PTEs) may be annotated with the selected physical address space distribution granularity, using an addressing mapping granularity (AMG) field of a page table entry, where the granularity may be, for example, a fine-grain distribution granularity or a coarse-grain distribution granularity.

Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344; B608045
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,282,309
Application Number:
15/441,532
OSTI ID:
1568306
Resource Relation:
Patent File Date: 02/24/2017
Country of Publication:
United States
Language:
English

References (15)

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