Logical memory address regions

Title: Logical memory address regions

Abstract

Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. Each logical memory address region may be dynamically configured at run-time to meet changing application needs of the system. Each logical memory address region may also be configured separately from the other logical memory address regions. Each logical memory address region may have associated parameters that identify region start address, region size, cell-level mode, physical-to-device mapping scheme, address masks, access permissions, wear-leveling data, encryption settings, and compression settings. These parameters may be stored in a table which may be used when processing memory access requests.

Inventors:: Farmahini-Farahani, Amin; Roberts, David A.

Publication Date:: 2019-04-09

Research Org.:: Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

Sponsoring Org.:: USDOE

OSTI Identifier:: 1568180

Patent Number(s):: 10,255,191

Application Number:: 15/133,033

Assignee:: Advanced Micro Devices, Inc. (Santa Clara, CA)

DOE Contract Number:: AC52-07NA27344

Resource Type:: Patent

Resource Relation:: Patent File Date: 04/19/2016

Country of Publication:: United States

Language:: English

Subject:: 97 MATHEMATICS AND COMPUTING

Citation Formats


                    Farmahini-Farahani, Amin, and Roberts, David A. Logical memory address regions.  United States: N. p., 2019. 
        Web.

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                    Farmahini-Farahani, Amin, & Roberts, David A. Logical memory address regions.  United States.

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                    Farmahini-Farahani, Amin, and Roberts, David A. Tue .  
        "Logical memory address regions".  United States.  https://www.osti.gov/servlets/purl/1568180.

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@article{osti_1568180,

  title        = {Logical memory address regions},

  author       = {Farmahini-Farahani, Amin and Roberts, David A.},

  abstractNote = {Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. Each logical memory address region may be dynamically configured at run-time to meet changing application needs of the system. Each logical memory address region may also be configured separately from the other logical memory address regions. Each logical memory address region may have associated parameters that identify region start address, region size, cell-level mode, physical-to-device mapping scheme, address masks, access permissions, wear-leveling data, encryption settings, and compression settings. These parameters may be stored in a table which may be used when processing memory access requests.},

  doi          = {},

  url          = {https://www.osti.gov/biblio/1568180},
  journal      = {},
number       = ,

  volume       = ,

  place        = {United States},

  year         = {2019},

  month        = {4}

}

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Works referenced in this record:

Dynamic SLC/MLC blocks allocations for non-volatile memory
patent, March 2013

Marotta, Giulio; De Santis, Luca; Vali, Tommaso
US Patent Document 8,407,400
https://doi.org/http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=8407400

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Title: Logical memory address regions

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Citation Formats

Dynamic SLC/MLC blocks allocations for non-volatile memory patent, March 2013

Dynamic SLC/MLC blocks allocations for non-volatile memory
patent, March 2013