Store operations to maintain cache coherence
Patent
·
OSTI ID:1373722
In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.
- Research Organization:
- INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- Assignee:
- INTERNATIONAL BUSINESS MACHINES CORPORATION
- Patent Number(s):
- 9,720,832
- Application Number:
- 14/671,050
- OSTI ID:
- 1373722
- Country of Publication:
- United States
- Language:
- English
The IBM RISC System/6000 processor: Hardware overview
|
journal | January 1990 |
| Automatic software cache coherence through vectorization | conference | January 1992 |
| Cohesion: a hybrid memory model for accelerators | conference | January 2010 |
Similar Records
Store operations to maintain cache coherence
Store-operate-coherence-on-value
Locality-aware and sharing-aware cache coherence for collections of processors
Patent
·
Tue Sep 12 00:00:00 EDT 2017
·
OSTI ID:1389845
Store-operate-coherence-on-value
Patent
·
Mon Nov 17 23:00:00 EST 2014
·
OSTI ID:1163975
Locality-aware and sharing-aware cache coherence for collections of processors
Patent
·
Tue Sep 14 00:00:00 EDT 2021
·
OSTI ID:1840447