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Locality-aware and sharing-aware cache coherence for collections of processors

Patent ·
OSTI ID:1840447
;
A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.
Research Organization:
Advanced Micro Devices, Inc., Santa Clara, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
11,119,923
Application Number:
15/440,979
OSTI ID:
1840447
Country of Publication:
United States
Language:
English

References (9)

QuickRelease: A throughput-oriented approach to release consistency on GPUs conference February 2014
Cache Coherence for GPU Architectures journal May 2014
Delayed consistency and its effects on the miss rate of parallel programs conference January 1991
Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors conference January 1995
Complexity-effective multicore coherence conference January 2012
Scope consistency conference January 1996
Active Memory Cube: A processing-in-memory architecture for exascale systems journal March 2015
The Midway Distributed Shared Memory System report March 1993
Lazy Release Consistency for Hardware-Coherent Multiprocessors. report December 1994

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