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Office of Scientific and Technical Information
 

Light-weight cache coherence for data processors with limited data sharing

Patent ·
OSTI ID:1469175
;
A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.
Research Organization:
Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
Sponsoring Organization:
USDOE
DOE Contract Number:
AC52-07NA27344
Assignee:
Advanced Micro Devices, Inc. (Santa Clara, CA)
Patent Number(s):
10,042,762
Application Number:
15/264,804
OSTI ID:
1469175
Country of Publication:
United States
Language:
English

References (6)

Cache coherence for GPU architectures conference February 2013
Active Memory Cube: A processing-in-memory architecture for exascale systems journal March 2015
The directory-based cache coherence protocol for the DASH multiprocessor journal May 1990
Dynamic self-invalidation: reducing coherence overhead in shared-memory multiprocessors conference January 1995
Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology journal August 2009
QuickRelease: A throughput-oriented approach to release consistency on GPUs conference February 2014

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