Store-operate-coherence-on-value
Patent
·
OSTI ID:1163975
A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.
- Research Organization:
- International Business Machines Corporation, Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,892,824
- Application Number:
- 12/986,652
- OSTI ID:
- 1163975
- Country of Publication:
- United States
- Language:
- English
Similar Records
Store operations to maintain cache coherence
Store operations to maintain cache coherence
Ordering of guarded and unguarded stores for no-sync I/O
Patent
·
Tue Aug 01 00:00:00 EDT 2017
·
OSTI ID:1373722
Store operations to maintain cache coherence
Patent
·
Tue Sep 12 00:00:00 EDT 2017
·
OSTI ID:1389845
Ordering of guarded and unguarded stores for no-sync I/O
Patent
·
Tue Jun 25 00:00:00 EDT 2013
·
OSTI ID:1086942