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Title: Store-operate-coherence-on-value

Abstract

A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

Inventors:
; ; ; ;
Publication Date:
Research Org.:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1163975
Patent Number(s):
8,892,824
Application Number:
12/986,652
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2011 Jan 07
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Chen, Dong, Heidelberger, Philip, Kumar, Sameer, Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Store-operate-coherence-on-value. United States: N. p., 2014. Web.
Chen, Dong, Heidelberger, Philip, Kumar, Sameer, Ohmacht, Martin, & Steinmacher-Burow, Burkhard. Store-operate-coherence-on-value. United States.
Chen, Dong, Heidelberger, Philip, Kumar, Sameer, Ohmacht, Martin, and Steinmacher-Burow, Burkhard. Tue . "Store-operate-coherence-on-value". United States. https://www.osti.gov/servlets/purl/1163975.
@article{osti_1163975,
title = {Store-operate-coherence-on-value},
author = {Chen, Dong and Heidelberger, Philip and Kumar, Sameer and Ohmacht, Martin and Steinmacher-Burow, Burkhard},
abstractNote = {A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {11}
}

Patent:

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