Ordering of guarded and unguarded stores for no-sync I/O
Patent
·
OSTI ID:1086942
A parallel computing system processes at least one store instruction. A first processor core issues a store instruction. A first queue, associated with the first processor core, stores the store instruction. A second queue, associated with a first local cache memory device of the first processor core, stores the store instruction. The first processor core updates first data in the first local cache memory device according to the store instruction. The third queue, associated with at least one shared cache memory device, stores the store instruction. The first processor core invalidates second data, associated with the store instruction, in the at least one shared cache memory. The first processor core invalidates third data, associated with the store instruction, in other local cache memory devices of other processor cores. The first processor core flushing only the first queue.
- Research Organization:
- International Business Machines Corporation (Armonk, NY)
- Sponsoring Organization:
- USDOE
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,473,683
- Application Number:
- 12/986,349
- OSTI ID:
- 1086942
- Country of Publication:
- United States
- Language:
- English
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