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Title: Conditional load and store in a shared memory

Abstract

A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.

Inventors:
;
Publication Date:
Research Org.:
International Business Machines Corporation, Armonk, NY (United States)
Sponsoring Org.:
USDOE
OSTI Identifier:
1169055
Patent Number(s):
8,949,539
Application Number:
12/697,799
Assignee:
International Business Machines Corporation (Armonk, NY) OSTI
DOE Contract Number:
B554331
Resource Type:
Patent
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Blumrich, Matthias A, and Ohmacht, Martin. Conditional load and store in a shared memory. United States: N. p., 2015. Web.
Blumrich, Matthias A, & Ohmacht, Martin. Conditional load and store in a shared memory. United States.
Blumrich, Matthias A, and Ohmacht, Martin. Tue . "Conditional load and store in a shared memory". United States. doi:. https://www.osti.gov/servlets/purl/1169055.
@article{osti_1169055,
title = {Conditional load and store in a shared memory},
author = {Blumrich, Matthias A and Ohmacht, Martin},
abstractNote = {A method, system and computer program product for implementing load-reserve and store-conditional instructions in a multi-processor computing system. The computing system includes a multitude of processor units and a shared memory cache, and each of the processor units has access to the memory cache. In one embodiment, the method comprises providing the memory cache with a series of reservation registers, and storing in these registers addresses reserved in the memory cache for the processor units as a result of issuing load-reserve requests. In this embodiment, when one of the processor units makes a request to store data in the memory cache using a store-conditional request, the reservation registers are checked to determine if an address in the memory cache is reserved for that processor unit. If an address in the memory cache is reserved for that processor, the data are stored at this address.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Tue Feb 03 00:00:00 EST 2015},
month = {Tue Feb 03 00:00:00 EST 2015}
}

Patent:

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