Direct match data flow memory for data driven computing

Patent · Wed Jan 01 04:00:00 EST 1997

OSTI ID:871176

Davidson, George S ^[1]; Grafe, Victor Gerald ^[2]

---

1. 8516 San Francisco NE., Albuquerque, NM 87109
2. 1909 Saturn Ct. NE., Albuquerque, NM 87112

A data flow computer and method of computing is disclosed which utilizes a data driven processor node architecture. The apparatus in a preferred embodiment includes a plurality of First-In-First-Out (FIFO) registers, a plurality of related data flow memories, and a processor. The processor makes the necessary calculations and includes a control unit to generate signals to enable the appropriate FIFO register receiving the result. In a particular embodiment, there are three FIFO registers per node: an input FIFO register to receive input information form an outside source and provide it to the data flow memories; an output FIFO register to provide output information from the processor to an outside recipient; and an internal FIFO register to provide information from the processor back to the data flow memories. The data flow memories are comprised of four commonly addressed memories. A parameter memory holds the A and B parameters used in the calculations; an opcode memory holds the instruction; a target memory holds the output address; and a tag memory contains status bits for each parameter. One status bit indicates whether the corresponding parameter is in the parameter memory and one status bit to indicate whether the stored information in the corresponding data parameter is to be reused. The tag memory outputs a "fire" signal (signal R VALID) when all of the necessary information has been stored in the data flow memories, and thus when the instruction is ready to be fired to the processor.

• Research Organization: AT & T CORP
• DOE Contract Number: AC04-76DP00789
• Assignee: Davidson, George S. (8516 San Francisco NE., Albuquerque, NM 87109);Grafe, Victor Gerald (1909 Saturn Ct. NE., Albuquerque, NM 87112)
• Patent Number(s): US 5675757
• OSTI ID: 871176
• Country of Publication: United States
• Language: English

Related Subjects

/712/711/
address
addressed
addressed memories
apparatus
appropriate
appropriate fifo
architecture
bit
bit indicates
bits
calculations
commonly
commonly addressed
comprised
computer
computing
contains
contains status
control
control unit
corresponding
corresponding data
corresponding parameter
data
data driven
data flow
data parameter
direct
direct match
disclosed
driven
driven computing
driven processor
embodiment
enable
fifo
fifo register
fifo registers
fire
fired
first-in-first-out
flow
flow computer
flow memories
form
generate
generate signals
holds
indicate
indicates
information
information form
input
input fifo
input information
instruction
internal
internal fifo
makes
match
match data
memories
memory
memory contains
memory holds
memory outputs
method
node
node architecture
opcode
opcode memory
output
output address
output fifo
output information
outputs
outside
outside recipient
outside source
parameter
parameter memory
parameters
particular
particular embodiment
plurality
preferred
preferred embodiment
processor
processor makes
processor node
provide
provide information
provide output
receive
receive input
receiving
recipient
register
register receiving
registers
related
related data
result
reused
signal
signals
source
status
status bit
status bits
stored
stored information
tag
tag memory
target
target memory
unit
utilizes
valid