Silicon on insulator self-aligned transistors
A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.
- Research Organization:
- The Regents of the University of California, Oakland, CA (United States) ; Lawrence Livermore National Laboratory (LLNL), Livermore, CA (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- W-7405-ENG-48
- Assignee:
- The Regents of the University of California (Oakland, CA)
- Patent Number(s):
- 6,649,977
- Application Number:
- 08/526,339
- OSTI ID:
- 1174590
- Country of Publication:
- United States
- Language:
- English
Ellipsometric Study of the Etch‐Stop Mechanism in Heavily Doped Silicon
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journal | January 1985 |
Vertically structured silicon membrane by electrochemical etching
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journal | April 1990 |
Study of electrochemical etch-stop for high-precision thickness control of silicon membranes
|
journal | April 1989 |
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