Multiprocessor switch with selective pairing
Patent
·
OSTI ID:1126499
System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus
- Research Organization:
- International Business Machines Corporation, Armonk, NY, USA
- Sponsoring Organization:
- USDOE
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,671,311
- Application Number:
- 13/027,882
- OSTI ID:
- 1126499
- Country of Publication:
- United States
- Language:
- English
A Genetic Algorithm for Reliability-Oriented Task Assignment With$widetildek$Duplications in Distributed Systems
|
journal | March 2006 |
The Stanford Hydra CMP
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journal | January 2000 |
Transactional Memory Coherence and Consistency
|
journal | March 2004 |
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