Multiprocessor system
Patent
·
OSTI ID:6456411
This patent describes an input/output system for a multiprocessor system of the kind in which a plurality of separate processor modules are interconnected for processing, each of the processor modules having a central processing unit and an associated main memory, at least pair of the processor modules each having an input/output channel with each such channel being independent of other such channels, the input/output system comprising: device controller for controlling the transfer of data between the pair of processor modules and a peripheral device, the device controller having multiple ports, with each such port being failure-independent of the other such ports and connected to a respective one of the input/output channels, each port including an enable latch operable in response to a disable command communicated to the port by the associated processor module to disable the port from any further data communication; the device controller including interface logic means responsive to signaling from a one of the processor modules for selecting one of the ports to the exclusion of the other of the ports for data transfers between the peripheral device and the one processor module connected to the selected port through its associated input/output channel; and interprocessor bus means communicating the pair of processor modules to one another for data transfer therebetween; each of processors modules being operable to provide a data communication path to the peripheral device for itself and for the other of the pair of processor modules.
- Assignee:
- Tandem Computers Inc., Cupertino, CA
- Patent Number(s):
- US 4672535
- OSTI ID:
- 6456411
- Country of Publication:
- United States
- Language:
- English
Similar Records
Input/output system for multiprocessors
Distributed multiprocess transaction processing system and method
Data error detection and device controller failure detection in an input/output system
Patent
·
Tue Apr 11 00:00:00 EDT 1989
·
OSTI ID:5970398
Distributed multiprocess transaction processing system and method
Patent
·
Tue Apr 04 00:00:00 EDT 1989
·
OSTI ID:5871888
Data error detection and device controller failure detection in an input/output system
Patent
·
Tue Jun 09 00:00:00 EDT 1987
·
OSTI ID:6315098
Related Subjects
99 GENERAL AND MISCELLANEOUS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERIZED CONTROL SYSTEMS
COMPUTERS
CONTROL SYSTEMS
DATA ACQUISITION SYSTEMS
DATA PROCESSING
DATA TRANSMISSION
DATA TRANSMISSION SYSTEMS
DIGITAL COMPUTERS
EQUIPMENT INTERFACES
FAILURES
FAULT TOLERANT COMPUTERS
MATHEMATICAL LOGIC
MEMORY DEVICES
PROCESSING
SIGNALS
990210* -- Supercomputers-- (1987-1989)
ARRAY PROCESSORS
COMMUNICATIONS
COMPUTER ARCHITECTURE
COMPUTERIZED CONTROL SYSTEMS
COMPUTERS
CONTROL SYSTEMS
DATA ACQUISITION SYSTEMS
DATA PROCESSING
DATA TRANSMISSION
DATA TRANSMISSION SYSTEMS
DIGITAL COMPUTERS
EQUIPMENT INTERFACES
FAILURES
FAULT TOLERANT COMPUTERS
MATHEMATICAL LOGIC
MEMORY DEVICES
PROCESSING
SIGNALS