skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: State recovery and lockstep execution restart in a system with multiprocessor pairing

Abstract

System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.

Inventors:
; ;
Publication Date:
Research Org.:
International Business Machines Corporation, Armonk, NY, USA
Sponsoring Org.:
USDOE
OSTI Identifier:
1117840
Patent Number(s):
8,635,492
Application Number:
13/027,932
Assignee:
International Business Machines Corporation (Armonk, NY)
DOE Contract Number:  
B554331
Resource Type:
Patent
Resource Relation:
Patent File Date: 2011 Feb 15
Country of Publication:
United States
Language:
English
Subject:
97 MATHEMATICS AND COMPUTING

Citation Formats

Gara, Alan, Gschwind, Michael K, and Salapura, Valentina. State recovery and lockstep execution restart in a system with multiprocessor pairing. United States: N. p., 2014. Web.
Gara, Alan, Gschwind, Michael K, & Salapura, Valentina. State recovery and lockstep execution restart in a system with multiprocessor pairing. United States.
Gara, Alan, Gschwind, Michael K, and Salapura, Valentina. Tue . "State recovery and lockstep execution restart in a system with multiprocessor pairing". United States. https://www.osti.gov/servlets/purl/1117840.
@article{osti_1117840,
title = {State recovery and lockstep execution restart in a system with multiprocessor pairing},
author = {Gara, Alan and Gschwind, Michael K and Salapura, Valentina},
abstractNote = {System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {2014},
month = {1}
}

Patent:

Save / Share:

Works referenced in this record:

A Genetic Algorithm for Reliability-Oriented Task Assignment With<tex>$widetildek$</tex>Duplications in Distributed Systems
journal, March 2006

  • Chiu, C. -C.; Hsu, C. -H.; Yeh, Y. -S.
  • IEEE Transactions on Reliability, Vol. 55, Issue 1
  • DOI: 10.1109/TR.2005.863797

The Stanford Hydra CMP
journal, January 2000

  • Hammond, L.; Hubbert, B. A.; Siu, M.
  • IEEE Micro, Vol. 20, Issue 2
  • DOI: 10.1109/40.848474

Transactional Memory Coherence and Consistency
journal, March 2004

  • Hammond, Lance; Olukotun, Kunle; Wong, Vicky
  • ACM SIGARCH Computer Architecture News, Vol. 32, Issue 2
  • DOI: 10.1145/1028176.1006711

Transactional memory: architectural support for lock-free data structures
journal, May 1993

  • Herlihy, Maurice; Moss, J. Eliot B.
  • ACM SIGARCH Computer Architecture News, Vol. 21, Issue 2
  • DOI: 10.1145/173682.165164