State recovery and lockstep execution restart in a system with multiprocessor pairing
System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.
- Research Organization:
- International Business Machines Corp., Armonk, NY (United States)
- Sponsoring Organization:
- USDOE
- DOE Contract Number:
- B554331
- Assignee:
- International Business Machines Corporation (Armonk, NY)
- Patent Number(s):
- 8,635,492
- Application Number:
- 13/027,932
- OSTI ID:
- 1117840
- Resource Relation:
- Patent File Date: 2011 Feb 15
- Country of Publication:
- United States
- Language:
- English
Method for updating operating system without memory reset
|
patent | September 2016 |
Redundant system control method
|
patent | November 2015 |
3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
|
patent | September 2014 |
3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
|
patent | August 2014 |
Similar Records
Scheduler for multiprocessor system switch with selective pairing
Multiprocessor system with multiple concurrent modes of execution