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State recovery and lockstep execution restart in a system with multiprocessor pairing

Patent ·
OSTI ID:1117840
; ;
System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory "nest" (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus. Each selectively paired processor core is includes a transactional execution facility, whereing the system is configured to enable processor rollback to a previous state and reinitialize lockstep execution in order to recover from an incorrect execution when an incorrect execution has been detected by the selective pairing facility.
Research Organization:
International Business Machines Corporation, Armonk, NY, USA
Sponsoring Organization:
USDOE
Assignee:
International Business Machines Corporation (Armonk, NY)
Patent Number(s):
8,635,492
Application Number:
13/027,932
OSTI ID:
1117840
Country of Publication:
United States
Language:
English

References (4)

Transactional memory: architectural support for lock-free data structures journal May 1993
A Genetic Algorithm for Reliability-Oriented Task Assignment With$widetildek$Duplications in Distributed Systems journal March 2006
The Stanford Hydra CMP journal January 2000
Transactional Memory Coherence and Consistency journal March 2004

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Related Subjects

97 MATHEMATICS AND COMPUTING